module vga_mem (clk, rd_addr, rd_data, wr_addr, wr_data, we);

parameter D_WIDTH   = 10;
parameter A_WIDTH   = 10;
parameter D_DEPTH   = 1<<A_WIDTH;

input  wire                 clk;
input  wire  [A_WIDTH-1:0]  rd_addr;
output wire  [D_WIDTH-1:0]  rd_data;

input  wire  [A_WIDTH-1:0]  wr_addr;
input  wire  [D_WIDTH-1:0]  wr_data;

input  wire                 we;

reg [D_WIDTH-1:0] mem [0:D_DEPTH];

assign rd_data = mem[rd_addr];

always @(posedge clk) begin
  if (we == 1'b1) begin
    mem[wr_addr] <= wr_data;
  end
end

endmodule
